EP2S130F1020I4 Datasheet, PDF (186/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Timing Model
Table 5–42. M-RAM Block Internal Timing Microparameters (Part 1 of 2) Note (1)
Symbol
Parameter
-3 Speed
Grade (2)
Min
(4)
Max
-3 Speed
Grade (3)
Min
(4)
Max
-4 Speed
Grade
Min
(5)
Max
-5 Speed
Grade
Unit
Min
(4)
Max
t_{M E G A R C}
Synchronous read cycle 1,866 2,774 1,866 2,911 1,777 3,189 1,777 3,716 ps
time
1,866
1,866
t_{M E G AW E R E S U} Write or read enable
144
151
165
192
ps
setup time before clock
165
t_{M E G AW E R E H} Write or read enable
39
40
44
52
ps
hold time after clock
44
t_{M E G A B E S U}
Byte enable setup time 50
52
57
67
ps
before clock
57
t_{M E G A B E H}
Byte enable hold time
39
40
44
52
ps
after clock
44
t_{M E G A DATA A S U} A port data setup time
50
52
57
67
ps
before clock
57
t_{M E G A DATA A H} A port data hold time
243
255
279
325
ps
after clock
279
t_{M E G A A D D R A S U} A port address setup
589
618
677
789
ps
time before clock
677
t_{M E G A A D D R A H} A port address hold time 241
253
277
322
ps
after clock
277
t_{M E G A DATA B S U} B port setup time before 50
52
57
67
ps
clock
57
t_{M E G A DATA B H} B port hold time after
243
255
279
325
ps
clock
279
t_{M E G A A D D R B S U} B port address setup
589
618
677
789
ps
time before clock
677
t_{M E G A A D D R B H} B port address hold time 241
253
277
322
ps
after clock
277
t_{M E G A D ATA C O 1}
Clock-to-output delay
when using output
registers
480 715 480 749 457 821 480 957 ps
480
t_{M E GA DATAC O 2} Clock-to-output delay 1,950 2,899 1,950 3,042 1,857 3,332 1,950 3,884 ps
without output registers
1,950
t_{M E G A C L K L}
Minimum clock low time 1,250
1,312
1,437
1,675
ps
1,437
5–40
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011