EP2S130F1020I4 Datasheet, PDF (697/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II and Stratix II GX Devices
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Refer to the Configuration & Testing chapter in volume 1 of the Stratix II
Device Handbook, or the Configuration & Testing chapter in volume 1 of the
Stratix II GX Device Handbook for the Stratix II family device
boundary-scan register lengths.
Figure 9–3 shows how test data is serially shifted around the periphery of
the IEEE Std. 1149.1 device.
Figure 9–3. Boundary-Scan Register
Internal Logic
Each peripheral
element is either an
I/O pin, dedicated
input pin, or
dedicated
configuration pin.
TAP Controller
TDI
TMS
TCK TRST (1) TDO
Boundary-Scan Cells of a Stratix II or Stratix II GX Device I/O Pin
The Stratix II or the Stratix II GX device 3-bit boundary-scan cell (BSC)
consists of a set of capture registers and a set of update registers. The
capture registers can connect to internal device data via the OUTJ, OEJ,
and PIN_IN signals, while the update registers connect to external data
through the PIN_OUT, and PIN_OE signals. The global control signals for
the IEEE Std. 1149.1 BST registers (such as shift, clock, and update) are
generated internally by the TAP controller. The MODE signal is generated
by a decode of the instruction register. The data signal path for the
boundary-scan register runs from the serial data in (SDI) signal to the
serial data out (SDO) signal. The scan register begins at the TDI pin and
ends at the TDO pin of the device.
Altera Corporation
January 2008
9–5
Stratix II Device Handbook, Volume 2