EP2S130F1020I4 Datasheet, PDF (757/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

High-Speed Board Layout Guidelines
Figure 11–25. Thevenin Parallel Fly-By Termination
V_CC
Receiver/Load
R₁
Source
Z_o = 50 Ω
Pad
R₂
Active Parallel Termination
Figure 11–26 shows an active parallel termination scheme, where the
terminating resistor (R_T = Z_o) is tied to a bias voltage (V_BIAS). In this
scheme, the voltage is selected so that the output drivers can draw current
from the high- and low-level signals. However, this scheme requires a
separate voltage source that can sink and source currents to match the
output transfer rates.
Figure 11–26. Active Parallel Termination
VBIAS
RT = Zo
S
Zo = 50 Ω
L
Stub
Altera Corporation
May 2007
11–21
Stratix II Device Handbook, Volume 2