EP2S130F1020I4 Datasheet, PDF (117/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Stratix II Architecture
Table 2–25. EP2S130 Differential Channels Note (1)
Package
Transmitter/ Total
Center Fast PLLs
Corner Fast PLLs (4)
Receiver Channels _{PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10}
780-pin
Transmitter 64 (2)
16
16
16
16
-
-
-
FineLine BGA
(3)
32
32
32
32
-
-
-
-
Receiver
68 (2)
17
17
17
17
-
-
-
-
(3)
34
34
34
34
-
-
-
1,020-pin
Transmitter 88 (2)
22
22
22
22
22
22
22
22
FineLine BGA
(3)
44
44
44
44
-
-
-
-
Receiver
92 (2)
23
23
23
23
23
23
23
23
(3)
46
46
46
46
-
-
-
-
1,508-pin
Transmitter 156 (2) 37
41
41
37
37
41
41
37
FineLine BGA
(3)
78
78
78
78
-
-
-
-
Receiver
156 (2) 37
41
41
37
37
41
41
37
(3)
78
78
78
78
-
-
-
-
Table 2–26. EP2S180 Differential Channels Note (1)
Package
Transmitter/ Total
Center Fast PLLs
Corner Fast PLLs (4)
Receiver Channels _{PLL 1 PLL 2 PLL 3 PLL 4 PLL 7 PLL 8 PLL 9 PLL 10}
1,020-pin
Transmitter 88 (2)
22
22
22
22
22
22
22
22
FineLine BGA
(3)
44
44
44
44
-
-
-
-
Receiver
92 (2)
23
23
23
23
23
23
23
23
(3)
46
46
46
46
-
-
-
-
1,508-pin
Transmitter 156 (2) 37
41
41
37
37
41
41
37
FineLine BGA
(3)
78
78
78
78
-
-
-
-
Receiver
156 (2) 37
41
41
37
37
41
41
37
(3)
78
78
78
78
-
-
-
-
Notes to Tables 2–21 to 2–26:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
(2) This is the maximum number of channels the PLLs can directly drive.
(3) This is the maximum number of channels if the device uses cross bank channels from the adjacent center PLL.
(4) The channels accessible by the center fast PLL overlap with the channels accessible by the corner fast PLL.
Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and
4 with the number of channels accessible by PLLs 7, 8, 9, and 10.
Altera Corporation
May 2007
2–99
Stratix II Device Handbook, Volume 1