EP2S130F1020I4 Datasheet, PDF (267/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
Table 1–3 shows the enhanced PLL and fast PLL features in Stratix II and
Stratix II GX devices.
Table 1–3. Stratix II and Stratix II GX PLL Features
Feature
Enhanced PLL
Fast PLL
Clock multiplication and division
m/(n × post-scale counter) (1) m/(n × post-scale counter) (2)
Phase shift
Down to 125-ps increments (3)
Clock switchover
v
PLL reconfiguration
v
Reconfigurable bandwidth
v
Spread-spectrum clocking
v
Programmable duty cycle
v
Number of clock outputs per PLL (5)
6
Number of dedicated external clock outputs Three differential or six
per PLL
single-ended
Down to 125-ps increments (3)
v (4)
v
v
v
4
(6)
Number of feedback clock inputs per PLL
1 (7)
Notes to Table 1–3:
(1) For enhanced PLLs, m and n range from 1 to 512 with 50% duty cycle. Post-scale counters range from 1 to 512 with
50% duty cycle. For non-50% duty-cycle clock outputs, post-scale counters range from 1 to 256.
(2) For fast PLLs, n can range from 1 to 4. The post-scale and m counters range from 1 to 32. For non-50% duty-cycle
clock outputs, post-scale counters range from 1 to 16.
(3) The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by eight. The
supported phase-shift range is from 125 to 250 ps. Stratix II and Stratix II GX devices can shift all output
frequencies in increments of at least 45. Smaller degree increments are possible depending on the frequency and
divide parameters. For non-50% duty cycle clock outputs post-scale counters range from 1 to 256.
(4) Stratix II and Stratix II GX fast PLLs only support manual clock switchover.
(5) The clock outputs can be driven to internal clock networks or to a pin.
(6) The PLL clock outputs of the fast PLLs can drive to any I/O pin to be used as an external clock output. For
high-speed differential I/O pins, the device uses a data channel to generate the transmitter output clock
(txclkout).
(7) If the design uses external feedback input pins, you will lose one (or two, if f_BIN is differential) dedicated output
clock pin.
Figure 1–1 shows a top-level diagram of Stratix II device and PLL
locations. Figure 1–2 shows a top-level diagram of Stratix II device and
PLL locations. See “Clock Control Block” on page 1–86 for more detail on
PLL connections to global and regional clocks networks.
Altera Corporation
July 2009
1–3
Stratix II Device Handbook, Volume 2