EP2S130F1020I4 Datasheet, PDF (706/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

IEEE Std. 1149.1 BST Operation Control
Figure 9–10 shows the capture, shift, and update phases of the EXTEST
mode.
Figure 9–10. IEEE Std. 1149.1 BST EXTEST Mode
Capture Phase
In the capture phase, the
signals at the pin, OEJ and
OUTJ, are loaded into the
capture registers. The CLOCK
signals is supplied by the TAP
controller’s CLOCKDR output.
Previously retained data in the
update registers drive the
PIN_IN, INJ, and allows the
I/O pin to tri-state or drive a
signal out.
A “1” in the OEJ update
register tri-states the output
buffer.
Shift and Update Phases
SDO
0
0
INJ
1
DQ
DQ
1
OEJ
0
1
DQ
0
DQ
1
OUTJ
0
1
DQ
0
DQ
1
Capture
Registers
Update
Registers
SDI
SHIFT
CLOCK
UPDATE
SDO
MODE
In the shift phase, the previously
captured signals at the pin, OEJ
and OUTJ, are shifted out of the
boundary-scan register via the
TDO pin using CLOCK. As data is
shifted out, the patterns for the
next test can be shifted in via the
TDI pin.
In the update phase, data is
transferred from the capture
registers to the update registers
using the UPDATE clock. The
update registers then drive the
PIN_IN, INJ, and allow the I/O pin
to tri-state or drive a signal out.
0
0
1
DQ
DQ
1
INJ
OEJ
0
1
DQ
0
DQ
1
OUTJ
0
1
DQ
0
DQ
1
Capture
Registers
Update
Registers
SDI
SHIFT
CLOCK
UPDATE
MODE
9–14
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008