EP2S130F1020I4 Datasheet, PDF (543/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–11. Two-Multiplier Adder Mode
shiftina
shiftinb
mult_round (1)
mult_saturate (1)
signa (1)
signb (1)
aclr[3..0]
clock[3..0]
ena[3..0]
Data A 1
Data B 1
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
Q1.15
Round/
Saturate
PRN
DQ
ENA
CLRN
Data A 2
Data B 2
DQ
ENA
CLRN
DQ
ENA
Q1.15
Round/
Saturate
PRN
DQ
ENA
CLRN
DQ
ENA
signb (2)
signa (2)
addnsub_round (2)
addnsub1 (2)
DQ
ENA
mult0_is_saturated (3)
Adder/
Subtractor/
Accumulator
1
Q1.15
Rounding
DQ
ENA
CLRN
Data Out 1
DQ
ENA
mult1_is_saturated (3)
shiftoutb shiftouta
Notes to Figure 6–11:
(1) These signals are not registered or registered once to match the data path pipeline.
(2) You can send these signals through a pipeline register. The pipeline length can be set to 1 or 2.
(3) These signals match the latency of the data path.
Complex Multiply
The DSP block can be configured to implement complex multipliers using
the two-multiplier adder mode. A single DSP block can implement one
18 × 18-bit complex multiplier or two 9 × 9-bit complex multipliers.
A complex multiplication can be written as:
(a + jb) × (c + jd) = ((a × c) – (b × d)) + j ((a × d) + (b × c))
To implement this complex multiplication within the DSP block, the real
part ((a × c) – (b × d)) is implemented using two multipliers feeding one
subtractor block while the imaginary part ((a × d) + (b × c)) is implemented
using another two multipliers feeding an adder block, for data up to
18-bits. Figure 6–12 shows an 18-bit complex multiplication. For data
widths up to 9-bits, a DSP block can perform two separate complex
Altera Corporation
January 2008
6–27
Stratix II Device Handbook, Volume 2