EP2S130F1020I4 Datasheet, PDF (517/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

6. DSP Blocks in Stratix II and
Stratix II GX Devices
SII52006-2.2
Introduction
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Stratix^® II and Stratix II GX devices have dedicated digital signal
processing (DSP) blocks optimized for DSP applications requiring high
data throughput. These DSP blocks combined with the flexibility of
programmable logic devices (PLDs), provide you with the ability to
implement various high performance DSP functions easily. Complex
systems such as CDMA2000, voice over Internet protocol (VoIP), high-
definition television (HDTV) require high performance DSP blocks to
process data. These system designs typically use DSP blocks as finite
impulse response (FIR) filters, complex FIR filters, fast Fourier transform
(FFT) functions, discrete cosine transform (DCT) functions, and
correlators.
Stratix II and Stratix II GX DSP blocks consist of a combination of
dedicated blocks that perform multiplication, addition, subtraction,
accumulation, and summation operations. You can configure these blocks
to implement arithmetic functions like multipliers, multiply-adders and
multiply-accumulators which are necessary for most DSP functions.
Along with the DSP blocks, the TriMatrix^TM memory structures in
Stratix II and Stratix II GX devices also support various soft multiplier
implementations. The combination of soft multipliers and dedicated DSP
blocks increases the number of multipliers available in Stratix II and
Stratix II GX devices and provides you with a wide variety of
implementation options and flexibility when designing your systems.
See the Stratix II Device Family Data Sheet in volume 1 of the Stratix II
Device Handbook or the Stratix II GX Device Family Data Sheet in volume 1
of the Stratix II GX Device Handbook for more information on Stratix II
and Stratix II GX devices, respectively.
DSP Block
Overview
Each Stratix II and Stratix II GX device has two to four columns of DSP
blocks that efficiently implement multiplication, multiply-accumulate
(MAC) and multiply-add functions. Figure 6–1 shows the arrangement of
one of the DSP block columns with the surrounding LABs. Each DSP
block can be configured to support:
■ Eight 9 × 9-bit multipliers
■ Four 18 × 18-bit multipliers
■ One 36 × 36-bit multiplier
Altera Corporation
6–1
January 2008