EP2S130F1020I4 Datasheet, PDF (61/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Stratix II Architecture
Figure 2–28. DSP Block Diagram for 18 × 18-Bit Configuration
Optional Serial Shift
Register Inputs from
Previous DSP Block
From the row
interface block
Optional Serial Shift
Register Outputs to
Next DSP Block
in the Column
PRN
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
PRN
DQ
ENA
CLRN
Multiplier Block
Adder Output Block
Q1.15
Round/
Saturate
PRN
DQ
ENA
CLRN
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
Output
Selection
Multiplexer
Adder/
Subtractor/
Accumulator
1
Q1.15
Round/
Saturate
Q1.15
Round/
Saturate
PRN
DQ
ENA
CLRN
Summation
Block
Adder
DQ
ENA
CLRN
Q1.15
Round/
Saturate
PRN
DQ
ENA
CLRN
Summation Stage
for Adding Four
Multipliers Together
Adder/
Subtractor/
Accumulator
2
Q1.15
Round/
Saturate
Q1.15
Round/
Saturate
PRN
DQ
ENA
CLRN
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
Optional Pipline
Register Stage
to MultiTrack
Interconnect
Altera Corporation
May 2007
2–43
Stratix II Device Handbook, Volume 1