EP2S130F1020I4 Datasheet, PDF (348/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Clocking
Figure 1–49. Stratix II GX Center Fast PLLs, Clock Pin and Logic Array Signal Connectivity to Global and
Regional Clock Networks Notes (1) and (2)
CLK0
CLK1
C0
Fast C1
PLL 1
C2
C3
Logic Array
Signal Input
To Clock
Network
CLK2
CLK3
C0
Fast C1
PLL 2
C2
C3
RCK0
RCK2
RCK4
RCK6
RCK1
RCK3
RCK5
RCK7
GCK0
GCK2
GCK1
GCK3
Notes to Figure 1–49:
(1) The redundant connection dots facilitate stitching of the clock networks to support the ability to drive two
quadrants with the same clock.
(2) The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. The global or regional clock input
can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
global or regional clock. An internally generated global signal cannot drive the PLL.
1–84
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009