EP2S130F1020I4 Datasheet, PDF (760/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Simultaneous Switching Noise
Figure 11–31. Differential Pair (LVDS & LVPECL) Termination
Stub
Z0 = 50 Ω
S
100 Ω
L
Z0 = 50 Ω
Stub
Figure 11–32 shows the differential pair fly-by termination scheme for the
LVDS and LVPECL standard.
Figure 11–32. Differential Pair (LVDS & LVPECL) Fly-By Termination
Receiver/Load
Z₀ = 50 Ω
+
S
Pads
100 Ω
Z₀ = 50 Ω
−
f
See the Board Design Guidelines for LVDS Systems White Paper for more
information on terminating differential signals.
Simultaneous
Switching Noise
As digital devices become faster, their output switching times decrease.
This causes higher transient currents in outputs as the devices discharge
load capacitances. These higher transient currents result in a board-level
phenomenon known as ground bounce.
Because many factors contribute to ground bounce, you cannot use a
standard test method to predict its magnitude for all possible PCB
environments. You can only test the device under a given set of
conditions to determine the relative contributions of each condition and
of the device itself. Load capacitance, socket inductance, and the number
of switching outputs are the predominant factors that influence the
magnitude of ground bounce in FPGAs.
Altera requires 0.01- to 0.1-F surface-mount capacitors in parallel to
reduce ground bounce. Add an additional 0.001-F capacitor in parallel
to these capacitors to filter high-frequency noise (>100 MHz). You can
also add 0.0047-F and 0.047-F capacitors.
11–24
Stratix II Device Handbook, Volume 2
Altera Corporation
May 2007