EP2S130F1020I4 Datasheet, PDF (119/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Stratix II Architecture
Figure 2–59. Stratix II Receiver Channel
Up to 1 Gbps ⁺
–
DQ
data retimed_data
DPA
DPA_clk
Eight Phase Clocks
8
refclk
Fast
PLL
Synchronizer
diffioclk
load_en
Data Realignment
Circuitry
Dedicated
Receiver
Interface
Data to R4, R24, C4, or
direct link interconnect
10
Regional or
global clock
f
An external pin or global or regional clock can drive the fast PLLs, which
can output up to three clocks: two multiplied high-speed clocks to drive
the SERDES block and/or external pin, and a low-speed clock to drive the
logic array. In addition, eight phase-shifted clocks from the VCO can feed
to the DPA circuitry.
For more information on the fast PLL, see the PLLs in Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook
or the Stratix II GX Device Handbook.
The eight phase-shifted clocks from the fast PLL feed to the DPA block.
The DPA block selects the closest phase to the center of the serial data eye
to sample the incoming data. This allows the source-synchronous
circuitry to capture incoming data correctly regardless of the channel-to-
channel or clock-to-channel skew. The DPA block locks to a phase closest
to the serial data phase. The phase-aligned DPA clock is used to write the
data into the synchronizer.
The synchronizer sits between the DPA block and the data realignment
and SERDES circuitry. Since every channel utilizing the DPA block can
have a different phase selected to sample the data, the synchronizer is
needed to synchronize the data to the high-speed clock domain of the
data realignment and the SERDES circuitry.
Altera Corporation
May 2007
2–101
Stratix II Device Handbook, Volume 1