EP2S130F1020I4 Datasheet, PDF (572/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Fast Passive Parallel Configuration
the chain. The configuration signals may require buffering to ensure
signal integrity and prevent clock skew problems. Ensure that the DCLK
and DATA lines are buffered for every fourth device. Because all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
All nSTATUS and CONF_DONE pins are tied together and if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the
devices release their nSTATUS pins after a reset time-out period
(maximum of 100 µs). After all nSTATUS pins are released and pulled
high, the MAX II device can try to reconfigure the chain without pulsing
nCONFIG low. If this option is turned off, the MAX II device must
generate a low-to-high transition (with a low pulse of at least 2 µs) on
nCONFIG to restart the configuration process.
In a multi-device FPP configuration chain, all Stratix II or Stratix II GX
devices in the chain must either enable or disable the decompression
and/or design security feature. You can not selectively enable the
decompression and/or design security feature for each device in the
chain because of the DATA and DCLK relationship. If the chain contains
devices that do not support design security, you should use a serial
configuration scheme.
If a system has multiple devices that contain the same configuration data,
tie all device nCE inputs to GND, and leave nCEO pins floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. Configuration
signals may require buffering to ensure signal integrity and prevent clock
skew problems. Ensure that the DCLK and DATA lines are buffered for
every fourth device. Devices must be the same density and package. All
devices start and complete configuration at the same time. Figure 7–5
shows multi-device FPP configuration when both Stratix II or
Stratix II GX devices are receiving the same configuration data.
7–20
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008