EP2S130F1020I4 Datasheet, PDF (300/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Advanced Features
Figure 1–18. Automatic Switchover Upon Clock Loss Detection
inclk0
inclk1
muxout
(1)
(2)
refclk
fbclk
clk0bad
(3)
(4)
clk1bad
lock
activeclock
clkloss
PLL Clock
Output
Notes to Figure 1–18:
(1) The number of clock edges before allowing switchover is determined by the counter setting.
(2) Switchover is enabled on the falling edge of INCLK1.
(3) The rising edge of FBCLK causes the VCO frequency to decrease.
(4) The rising edge of REFCLK starts the PLL lock process again, and the VCO frequency increases.
1–36
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009