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EP2S130F1020I4 Datasheet, PDF (336/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1 | |||
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Clocking
Table 1â21. Stratix II GX Device PLLs and PLL Clock Pin Drivers (Part 2 of 2)
All Devices
EP2SGX60 to EP2SGX130 Devices
Input Pin
Fast PLLs
Enhanced
PLLs
Fast PLLs
Enhanced
PLLs
PLL12_FB
PLL_ENA
FPLL7CLK (3)
FPLL8CLK (3)
FPLL9CLK (3)
FPLL10CLK (3)
1 2 3 (1) 4 (1) 5 6 7 8 9 (1) 10 (1) 11 12
v
vv
vvv v
vv
v
v
Notes to Table 1â21:
(1) PLLs 3, 4, 9, and 10 are not available in Stratix II GX devices.
(2) Clock connection is available. For more information about the maximum frequency, contact Altera Applications.
(3) This is a dedicated high-speed clock input. For more information about the maximum frequency, contact Altera
Applications.
(4) Input pins CLK[11..8] are not available in Stratix II GX devices.
CLK(n) Pin Connectivity to Global Clock Networks
In Stratix II and Stratix II GX devices, the clk(n) pins can also feed the
global clock network. Table 1â22 shows the clk(n) pin connectivity to
global clock networks.
Table 1â22. CLK(n) Pin Connectivity to Global Clock Network
Clock
Resource
CLK(n) pin
4
5
6
7
12 13 14 15
GCLK4
GCLK5
GCLK6
GCLK7
GCLK12
GCLK13
GCLK14
GCLK15
v
v
v
v
v
v
v
v
1â72
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
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