English
Language : 

EP2S130F1020I4 Datasheet, PDF (361/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1
SII52002-4.5
Introduction
TriMatrix
Memory
Overview
2. TriMatrix Embedded
Memory Blocks in Stratix II
and Stratix II GX Devices
Stratix® II and Stratix II GX devices feature the TriMatrix™ memory
structure, consisting of three sizes of embedded RAM blocks that
efficiently address the memory needs of FPGA designs.
TriMatrix memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and
512-Kbit M-RAM blocks, which are each configurable to support many
features. TriMatrix memory provides up to 9 megabits of RAM at up to
550 MHz operation, and up to 16 terabits per second of total memory
bandwidth per device. This chapter describes TriMatrix memory blocks,
modes, and features.
The TriMatrix architecture provides complex memory functions for
different applications in FPGA designs. For example, M512 blocks are
used for first-in first-out (FIFO) functions and clock domain buffering
where memory bandwidth is critical; M4K blocks are ideal for
applications requiring medium-sized memory, such as asynchronous
transfer mode (ATM) cell processing; and M-RAM blocks are suitable for
large buffering applications, such as internet protocol (IP) packet
buffering and system cache.
The TriMatrix memory blocks support various memory configurations,
including single-port, simple dual-port, true dual-port (also known as
bidirectional dual-port), shift register, and read-only memory (ROM)
modes. The TriMatrix memory architecture also includes advanced
features and capabilities, such as parity-bit support, byte enable support,
pack mode support, address clock enable support, mixed port width
support, and mixed clock mode support.
When applied to input registers, the asynchronous clear signal for the
TriMatrix embedded memory immediately clears the input registers.
However, the output of the memory block does not show the effects until
the next clock edge. When applied to output registers, the asynchronous
clear signal clears the output registers and the effects are seen
immediately.
Altera Corporation
2–1
January 2008