EP2S130F1020I4 Datasheet, PDF (341/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
Figure 1–47. Stratix II and Stratix II GX Top and Bottom Enhanced PLLs, Clock Pin and Logic Array Signal
Connectivity to Global and Regional Clock Networks Notes (1) and (2)
CLK13 CLK15
CLK12
PLL11_FB
CLK14
PLL5_FB
PLL11_OUT[2..0]p
PLL11_OUT[2..0]n
Regional
Clocks
RCLK27
RCLK26
RCLK25
RCLK24
Global
Clocks
Regional
Clocks
RCLK8
RCLK9
RCLK10
RCLK11
PLL12_OUT[2..0]p
PLL12_OUT[2..0]n
PLL 11
PLL 5
c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5
PLL5_OUT[2..0]p
PLL5_OUT[2..0]n
RCLK31
RCLK30
RCLK29
RCLK28
G15
G14
G13
G12
G4
G5
G6
G7
c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5
PLL 12
PLL 6
RCLK12
RCLK13
RCLK14
RCLK15
PLL6_OUT[2..0]p
PLL6_OUT[2..0]n
PLL12_FB
CLK4
CLK6
PLL6_FB
CLK5
CLK7
Notes to Figure 1–47:
(1) The redundant connection dots facilitate stitching of the clock networks to support the ability to drive two
quadrants with the same clock.
(2) The enhanced PLLs can also be driven through the global or regional clock networks. The global or regional clock
input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a
clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
global or regional clock. An internally generated global signal cannot drive the PLL.
Altera Corporation
July 2009
1–77
Stratix II Device Handbook, Volume 2