EP2S130F1020I4 Datasheet, PDF (532/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Architecture
Pipeline Registers
The output from the multiplier can feed a pipeline register or this register
can be bypassed. Pipeline registers may be implemented for any
multiplier size and increase the DSP block’s maximum performance,
especially when using the subsequent DSP block adder stages. Pipeline
registers split up the long signal path between the
adder/subtractor/accumulator block and the adder/output block,
creating two shorter paths.
Adder/Output Block
The adder/output block has the following elements:
■ An adder/subtractor/accumulator block
■ A summation block
■ An output select multiplexer
■ Output registers
Figure 6–7 shows the adder/output block architecture.
The adder/output block can be configured as:
■ An output interface
■ An accumulator which can be optionally loaded
■ A one-level adder
■ A two-level adder with dynamic addition/subtraction control on the
first-level adder
■ The final stage of a 36-bit multiplier, 9 × 9 complex multiplier, or
18 × 18 complex multiplier
The output select multiplexer sets the output configuration of the DSP
block. The output registers can be used to register the output of the
adder/output block.
1 The adder/output block cannot be used independently from the
multiplier.
6–16
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008