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EP2S130F1020I4 Datasheet, PDF (303/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1 | |||
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PLLs in Stratix II and Stratix II GX Devices
Figure 1â21. Switchover Simulation Note (1)
10
9
8
7
6
PLL Output
Frequency (x10 MHz)
5
4
3
2
1
0
0
5
10
15
20
25
30
35
40
Time (μs)
Note to Figure 1â21:
(1) This simulation was performed under the following conditions: the n counter is set to 2, the m counter is set to 16,
and the output counter is set to 8. Therefore, the VCO operates at 800 MHz for the 100-MHz input references and at
528 MHz for the 66-MHz reference input.
Lock Signal-Based Switchover
The lock circuitry can initiate the automatic switchover. This is useful for
cases where the input clock is still clocking, but its characteristics have
changed so that the PLL is not locked to it. The switchover enable is based
on both the gated and ungated lock signals. If the ungated lock is low, the
switchover is not enabled until the gated lock has reached its terminal
count. You must activate the switchover enable if the gated lock is high,
but the ungated lock goes low. The switchover timing for this mode is
similar to the waveform shown in Figure 1â20 for clkswitch control,
except the switchover enable replaces clkswitch. Figure 1â17 shows
the switchover enable circuit when controlled by lock and gated lock.
Figure 1â22. Switchover Enable Circuit
Lock
Gated Lock
Switchover
Enable
Altera Corporation
July 2009
1â39
Stratix II Device Handbook, Volume 2
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