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EP2S130F1020I4 Datasheet, PDF (252/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1 | |||
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Contents
Stratix II Device Handbook, Volume 2
VCCD ................................................................................................................................................................................................................... 1â58
External Clock Output Power ...................................................................................................... 1â58
Guidelines ........................................................................................................................................ 1â61
PLL Specifications ................................................................................................................................ 1â62
Clocking ................................................................................................................................................ 1â62
Global and Hierarchical Clocking ................................................................................................ 1â62
Clock Sources Per Region .............................................................................................................. 1â64
Clock Input Connections ............................................................................................................... 1â69
Clock Source Control For Enhanced PLLs .................................................................................. 1â73
Clock Source Control for Fast PLLs ............................................................................................. 1â73
Delay Compensation for Fast PLLs ............................................................................................. 1â75
Clock Output Connections ............................................................................................................ 1â76
Clock Control Block ............................................................................................................................. 1â86
clkena Signals .................................................................................................................................. 1â90
Conclusion ............................................................................................................................................ 1â91
Referenced Documents ....................................................................................................................... 1â91
Document Revision History ............................................................................................................... 1â92
Section II. Memory
Revision History ..................................................................................................................... Section IIâ1
Chapter 2. TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 2â1
TriMatrix Memory Overview .............................................................................................................. 2â1
Parity Bit Support ............................................................................................................................. 2â3
Byte Enable Support ........................................................................................................................ 2â4
Pack Mode Support .......................................................................................................................... 2â7
Address Clock Enable Support ...................................................................................................... 2â8
Memory Modes ...................................................................................................................................... 2â9
Single-Port Mode ............................................................................................................................ 2â10
Simple Dual-Port Mode ................................................................................................................. 2â12
True Dual-Port Mode ..................................................................................................................... 2â15
Shift-Register Mode ....................................................................................................................... 2â18
ROM Mode ...................................................................................................................................... 2â20
FIFO Buffers Mode ......................................................................................................................... 2â20
Clock Modes ......................................................................................................................................... 2â20
Independent Clock Mode .............................................................................................................. 2â21
Input/Output Clock Mode ........................................................................................................... 2â23
Read/Write Clock Mode ............................................................................................................... 2â26
Single-Clock Mode ......................................................................................................................... 2â28
Designing With TriMatrix Memory .................................................................................................. 2â31
Selecting TriMatrix Memory Blocks ............................................................................................ 2â31
Synchronous and Pseudo-Asynchronous Modes ...................................................................... 2â32
Power-up Conditions and Memory Initialization ..................................................................... 2â32
Read-During-Write Operation at the Same Address ..................................................................... 2â33
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Altera Corporation
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