EP2S130F1020I4 Datasheet, PDF (569/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
Data is continuously clocked into the target device until CONF_DONE goes
high. The CONF_DONE pin goes high one byte early in parallel
configuration (FPP and PPA) modes. The last byte is required for serial
configuration (AS and PS) modes. After the device has received the next
to last byte of the configuration data successfully, it releases the
open-drain CONF_DONE pin, which is pulled high by an external 10-k
pull-up resistor. A low-to-high transition on CONF_DONE indicates
configuration is complete and initialization of the device can begin. The
CONF_DONE pin must have an external 10-k pull-up resistor in order for
the device to initialize.
In Stratix II and Stratix II GX devices, the initialization clock source is
either the internal oscillator (typically 10 MHz) or the optional CLKUSR
pin. By default, the internal oscillator is the clock source for initialization.
If the internal oscillator is used, the Stratix II or Stratix II GX device
provides itself with enough clock cycles for proper initialization.
Therefore, if the internal oscillator is the initialization clock source,
sending the entire configuration file to the device is sufficient to configure
and initialize the device. Driving DCLK to the device after configuration is
complete does not affect device operation.
You can also synchronize initialization of multiple devices or to delay
initialization with the CLKUSR option. The Enable user-supplied start-up
clock (CLKUSR) option can be turned on in the Quartus II software from
the General tab of the Device & Pin Options dialog box. Supplying a
clock on CLKUSR does not affect the configuration process. The
CONF_DONE pin goes high one byte early in parallel configuration (FPP
and PPA) modes. The last byte is required for serial configuration (AS and
PS) modes. After the CONF_DONE pin transitions high, CLKUSR is enabled
after the time specified as t_CD2CU. After this time period elapses, Stratix II
and Stratix II GX devices require 299 clock cycles to initialize properly
and enter user mode. Stratix II and Stratix II GX devices support a
CLKUSR f_MAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it is high because of an external 10-k
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. The MAX II device must be
able to detect this low-to-high transition, which signals the device has
Altera Corporation
January 2008
7–17
Stratix II Device Handbook, Volume 2