EP2S130F1020I4 Datasheet, PDF (696/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

IEEE Std. 1149.1 Boundary-Scan Register
Figure 9–2 shows a functional model of the IEEE Std. 1149.1 circuitry.
Figure 9–2. IEEE Std. 1149.1 Circuitry
Instruction Register (1)
TDI
UPDATEIR
CLOCKIR
SHIFTIR
TDO
TMS
TCLK
TRST (1)
TAP
Controller
UPDATEDR
CLOCKDR
SHIFTDR
Instruction Decode
Data Registers
Bypass Register
Boundary-Scan Register (1)
a
Device ID Register
ICR Registers
Note to Figure 9–2:
(1) Refer to the appropriate device data sheet for register lengths.
IEEE Std. 1149.1 boundary-scan testing is controlled by a test access port
(TAP) controller. For more information on the TAP controller, refer to
“IEEE Std. 1149.1 BST Operation Control” on page 9–7. The TMS and TCK
pins operate the TAP controller, and the TDI and TDO pins provide the
serial path for the data registers. The TDI pin also provides data to the
instruction register, which then generates control logic for the data
registers.
IEEE Std. 1149.1
Boundary-Scan
Register
The boundary-scan register is a large serial shift register that uses the TDI
pin as an input and the TDO pin as an output. The boundary-scan register
consists of 3-bit peripheral elements that are associated with Stratix II or
Stratix II GX I/O pins. You can use the boundary-scan register to test
external pin connections or to capture internal data.
9–4
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008