EP2S130F1020I4 Datasheet, PDF (129/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Configuration & Testing
Operating Modes
The Stratix II architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power-up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode. Normal device
operation is called user mode.
SRAM configuration elements allow Stratix II devices to be reconfigured
in-circuit by loading new configuration data into the device. With real-
time reconfiguration, the device is forced into command mode with a
device pin. The configuration process loads different configuration data,
reinitializes the device, and resumes user-mode operation. You can
perform in-field upgrades by distributing new configuration files either
within the system or remotely.
PORSEL is a dedicated input pin used to select POR delay times of 12 ms
or 100 ms during power-up. When the PORSEL pin is connected to
ground, the POR time is 100 ms; when the PORSEL pin is connected to
V_CC, the POR time is 12 ms.
The nIO PULLUP pin is a dedicated input that chooses whether the
internal pull-ups on the user I/O pins and dual-purpose configuration
I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS,
RUnLU, PGM[2..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR) are on or
off before and during configuration. A logic high (1.5, 1.8, 2.5, 3.3 V) turns
off the weak internal pull-ups, while a logic low turns them on.
Stratix II devices also offer a new power supply, V_CCPD, which must be
connected to 3.3 V in order to power the 3.3-V/2.5-V buffer available on
the configuration input pins and JTAG pins. V_CCPD applies to all the JTAG
input pins (TCK, TMS, TDI, and TRST) and the configuration input pins
when VCCSEL is connected to ground. See Table 3–4 for more information
on the pins affected by VCCSEL.
The VCCSEL pin allows the V_CCIO setting (of the banks where the
configuration inputs reside) to be independent of the voltage required by
the configuration inputs. Therefore, when selecting the V_CCIO, the V_IL and
V_IH levels driven to the configuration inputs do not have to be a concern.
Altera Corporation
May 2007
3–5
Stratix II Device Handbook, Volume 1