EP2S130F1020I4 Datasheet, PDF (313/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
Figure 1–30. Effect of High Bandwidth on Clock Switchover
160
155
Initial Lock
150
Input Clock Stops
Re-lock
145
Frequency (MHz) ₁₄₀
135
Switchover
130
125
0
2
4
6
8
10
12
14
16
18
20
Time (μs)
Implementation
Traditionally, external components such as the VCO or loop filter control
a PLL’s bandwidth. Most loop filters are made up of passive components
such as resistors and capacitors that take up unnecessary board space and
increase cost. With Stratix II and Stratix II GX PLLs, all the components
are contained within the device to increase performance and decrease
cost.
Stratix II and Stratix II GX device PLLs implement reconfigurable
bandwidth by giving you control of the charge pump current and loop
filter resistor (R) and high-frequency capacitor C_H values (see Table 1–16).
The Stratix II and Stratix II GX device enhanced PLL bandwidth ranges
from 130 kHz to 16.9 MHz. The Stratix II and Stratix II GX device fast PLL
bandwidth ranges from 1.16 to 28 MHz.
Altera Corporation
July 2009
1–49
Stratix II Device Handbook, Volume 2