EP2S130F1020I4 Datasheet, PDF (493/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
The deserializer, like the serializer, can also be bypassed to support DDR
(2) and SDR (1) operations. The DPA and data realignment circuit
cannot be used when the deserializer is bypassed. The IOE contains two
data input registers that can operate in DDR or SDR mode. The clock
source for the registers in the IOE can come from any routing resource,
from the fast PLL, or from the enhanced PLL. Figure 5–7 shows the
bypass path.
Figure 5–7. Deserializer Bypass
rx_in
DPA
Circuitry
IOE Supports SDR, DDR, or
Non-Registered Data Path
IOE
Deserializer
PLD Logic
Array
Receiver Data Realignment Circuit
The data realignment circuit aligns the word boundary of the incoming
data by inserting bit latencies into the serial stream. An optional
RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each
receiver independently controlled from the internal logic. The data slips
one bit for every pulse on the RX_CHANNEL_DATA_ALIGN port. The
following are requirements for the RX_CHANNEL_DATA_ALIGN port:
■ The minimum pulse width is one period of the parallel clock in the
logic array.
■ The minimum low time between pulses is one period of parallel
clock.
■ There is no maximum high or low time.
■ Valid data is available two parallel clock cycles after the rising edge
of RX_CHANNEL_DATA_ALIGN.
Altera Corporation
January 2008
5–9
Stratix II Device Handbook, Volume 2