EP2S130F1020I4 Datasheet, PDF (451/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Selectable I/O Standards in Stratix II and Stratix II GX Devices
Figures 4–12 and 4–13 shows details on differential SSTL-18 termination.
Stratix II and Stratix II GX devices support differential SSTL-18 I/O
standards in pseudo-differential mode, which is implemented by using
two SSTL-18 single-ended buffers.
The Quartus II software only supports pseudo-differential standards on
the INCLK, FBIN and EXTCLK ports of enhanced PLL, as well as on DQS
pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is
used. Two single-ended output buffers are automatically programmed to
have opposite polarity so as to implement a pseudo-differential output. A
proper V_REF voltage is required for the two single-ended input buffers to
implement a pseudo-differential input. In this case, only the positive
polarity input is used in the speed path while the negative input is not
connected internally. In other words, only the non-inverted pin is
required to be specified in your design, while the Quartus II software
automatically generates the inverted pin for you.
Although the Quartus II software does not support pseudo-differential
SSTL-18 I/O standards on the left and right I/O banks, you can
implement these standards at these banks. You need to create two pins in
the designs and configure the pins with single-ended SSTL-18 standards.
However, this is limited only to pins that support the differential pin-pair
I/O function and is dependent on the single-ended SSTL-18 standards
support at these banks.
Figure 4–12. Differential SSTL-18 Class I Termination
VTT = 0.9 V VTT = 0.9 V
Differential
Transmitter
25 Ω
50 Ω
Z0 = 50 Ω
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
Altera Corporation
January 2008
4–13
Stratix II Device Handbook, Volume 2