EP2S130F1020I4 Datasheet, PDF (526/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Architecture
dedicated shift register chain spans a single column but longer shift
register chains requiring multiple columns can be implemented using
regular FPGA routing resources. Therefore, this shift register chain can be
of any length up to 768 registers in the largest member of the Stratix II or
Stratix II GX device family.
Shift registers are useful in DSP functions like FIR filters. When
implementing 9 × 9 and 18 × 18 multipliers, you do not need external
logic to create the shift register chain because the input shift registers are
internal to the DSP block. This implementation significantly reduces the
LE resources required, avoids routing congestion, and results in
predictable timing.
Stratix II and Stratix II GX DSP blocks allow you to dynamically select
whether a particular multiplier operand is fed by regular data input or
the dedicated shift register input using the sourcea and sourceb
signals. A logic 1 value on the sourcea signal indicates that data A is fed
by the dedicated scan-chain; a logic 0 value indicates that it is fed by
regular data input. This feature allows the implementation of a
dynamically loadable shift register where the shift register operates
normally using the scan-chains and can also be loaded dynamically in
parallel using the data input value.
6–10
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008