EP2S130F1020I4 Datasheet, PDF (218/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Timing Model
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 4 of 5) Note (1)
I/O Standard
Drive
Strength
1.8-V LVTTL
3.3-V LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.2-V HSTL (2)
1.5-V HSTL
Class I
1.8-V HSTL
Class I
1.8-V HSTL
Class II
Differential
SSTL-2 Class I
Differential
SSTL-2 Class II
Differential
SSTL-18 Class I
Differential
SSTL-18 Class II
1.8-V Differential
HSTL Class I
1.8-V Differential
HSTL Class II
1.5-V Differential
HSTL Class I
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
Column I/O Pins (MHz)
-3
-4
-5
700
550
450
350
350
300
550
450
400
600
500
500
600
550
500
560
400
350
550
500
450
280
-
-
600
550
500
650
600
600
500
500
450
600
500
500
600
550
500
560
400
350
550
500
450
650
600
600
500
500
450
600
550
500
Row I/O Pins (MHz) Clock Outputs (MHz)
-3
-4 -5 -3 -4 -5
700
550 450 700 550 450
350
350 300 350 350 300
550
450 400 550 450 400
600
500 500 600 500 500
600
550 500 600 550 500
590
400 350 450 400 350
-
-
- 550 500 450
-
-
- 280 -
-
600
550 500 600 550 500
650
600 600 650 600 600
-
-
- 500 500 450
600
500 500 600 500 500
600
550 500 600 550 500
590
400 350 560 400 350
-
-
- 550 500 450
650
600 600 650 600 600
-
-
- 500 500 450
600
550 500 600 550 500
5–72
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011