EP2S130F1020I4 Datasheet, PDF (609/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
f
100 ms or 2 ms, depending on its PORSEL pin setting. If the PORSEL pin
is connected to GND, the POR delay is 100 ms. If the PORSEL pin is
connected to V_CC, the POR delay is 2 ms. During this time, the
configuration device drives its OE pin low. This low signal delays
configuration because the OE pin is connected to the target device’s
nSTATUS pin.
1
When selecting a POR time, you need to ensure that the device
completes power-up before the enhanced configuration device
exits POR. Altera recommends that you choose a POR time for
the Stratix II or Stratix II GX device of 12 ms, while selecting a
POR time for the enhanced configuration device of 100 ms.
When both devices complete POR, they release their open-drain OE or
nSTATUS pin, which is then pulled high by a pull-up resistor. Once the
device successfully exits POR, all user I/O pins continue to be tri-stated.
If nIO_pullup is driven low during power-up and configuration, the
user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the DC & Switching
Characteristics chapter in volume 2 of the Stratix II Device Handbook or the
DC & Switching Characteristics chapter in volume 2 of the Stratix II GX
Device Handbook.
When the power supplies have reached the appropriate operating
voltages, the target device senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration, and initialization. While nCONFIG or
nSTATUS are low, the device is in reset. The beginning of configuration
can be delayed by holding the nCONFIG or nSTATUS pin low.
1
To begin configuration, power the V_CCINT, V_CCIO, and V_CCPD
voltages (for the banks where the configuration and JTAG pins
reside) to the appropriate voltage levels.
When nCONFIG goes high, the device comes out of reset and releases the
nSTATUS pin, which is pulled high by a pull-up resistor. Enhanced
configuration and EPC2 devices have an optional internal pull-up resistor
on the OE pin. This option is available in the Quartus II software from the
General tab of the Device & Pin Options dialog box. If this internal
pull-up resistor is not used, an external 10-k pull-up resistor on the
OE-nSTATUS line is required. Once nSTATUS is released, the device is
ready to receive configuration data and the configuration stage begins.
Altera Corporation
January 2008
7–57
Stratix II Device Handbook, Volume 2