EP2S130F1020I4 Datasheet, PDF (274/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Enhanced PLLs
Figure 1–6. Enhanced PLL Ports
(1)
(2), (3)
(2), (3)
pllena
inclk0
inclk1
scanclk
scanwrite
scanread
scandata
fbin
clkswitch
areset
pfdena
C[5..0]
(4)
locked
clkloss
activeclock
scandataout
clkbad[1..0]
scandone
Physical Pin
Signal Driven by Internal Logic
Signal Driven to Internal Logic
Internal Clock Signal
pll_out0p
(5)
pll_out0n
(5)
pll_out1p
(5)
pll_out1n
(5)
pll_out2p
(5)
pll_out2n
(5)
Notes to Figure 1–6:
(1) Enhanced and fast PLLs share this input pin.
(2) These are either single-ended or differential pins.
(3) The primary and secondary clock input can be fed from any one of four clock pins located on the same side of the
device as the PLL.
(4) Can drive to the global or regional clock networks or the dedicated external clock output pins.
(5) These dedicated output clocks are fed by the C[5..0] counters.
Tables 1–4 and 1–5 describe all the enhanced PLL ports.
Table 1–4. Enhanced PLL Input Signals (Part 1 of 2)
Port
inclk0
inclk1
fbin
pllena
clkswitch
Description
Source
Primary clock input to the PLL.
Pin or another PLL
Secondary clock input to the PLL. Pin or another PLL
External feedback input to the PLL. Pin
Enable pin for enabling or disabling
all or a set of PLLs. Active high.
Switch-over signal used to initiate
external clock switch-over control.
Active high.
Pin
Logic array
Destination
n counter
n counter
PFD
General PLL control
signal
PLL switch-over circuit
1–10
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009