EP2S130F1020I4 Datasheet, PDF (413/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

External Memory Interfaces in Stratix II and Stratix II GX Devices
Table 3–5. Stratix II GX DQS and DQ Bus Mode Support Note (1)
Device
Package
EP2SGX30C 780-pin FineLine BGA
EP2SGX30D
EP2SGX60C 780-pin FineLine BGA
EP2SGX60D
EP2SGX60E 1,152-pin FineLine BGA
EP2SGX90E 1,152-pin FineLine BGA
EP2SGX90F 1,508-pin FineLine BGA
EP2SGX130G 1,508-pin FineLine BGA
Number of
×4 Groups
18
18
36
36
36
36
Number of
Number of
Number of
×8/×9 Groups ×16/×18 Groups ×32/×36 Groups
8
4
0
8
4
0
18
8
4
18
8
4
18
8
4
18
8
4
Note to Table 3–5:
(1) Check the pin table for each DQS/DQ group in the different modes.
Table 3–6. Stratix II GX Non-DQS and DQ Bus Mode Support Note (1)
Device
EP2SGX30
EP2SGX60
EP2SGX90
EP2SGX130
Package
780-pin FineLine BGA
780-pin FineLine BGA
1,152-pin FineLine BGA
1,152-pin FineLine BGA
1,508-pin FineLine BGA
1,508-pin FineLine BGA
Number of
×4 Groups
18
18
25
25
25
25
Number of
Number of
Number of
×8/×9 Groups ×16/×18 Groups ×32/×36 Groups
8
4
2
8
4
2
13
6
3
13
6
3
12
6
3
12
6
3
Note to Table 3–6:
(1) Check the pin table for each DQS/DQ group in the different modes.
1 To support the RLDRAM II QVLD pin, some of the unused ×4
DQS pins, whose DQ pins were combined to make the bigger
×8/×9, ×16/×18, or ×32/×36 groups, are listed as DQVLD pins
in the Stratix II or Stratix II GX pin table. DQVLD pins are for
input-only operations. The signal coming into this pin can be
captured by the shifted DQS signal like any of the DQ pins.
Altera Corporation
January 2008
3–17
Stratix II Device Handbook, Volume 2