EP2S130F1020I4 Datasheet, PDF (302/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Advanced Features
switchover circuit is edge-sensitive, the falling edge of the clkswitch
signal does not cause the circuit to switch back from inclk1 to inclk0.
When the clkswitch signal goes high again, the process repeats.
clkswitch and automatic switch only work if the clock being switched
to is available. If the clock is not available, the state machine waits until
the clock is available.
Figure 1–20. Clock Switchover Using the CLKSWITCH Control Note (1)
inclk0
inclk1
muxout
clkswitch
activeclock
clkloss
clk0bad
clk1bad
Note to Figure 1–20:
(1) Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate a manual clock
switchover event. Failing to meet this requirement causes the clock switchover to not function properly.
Figure 1–21 shows a simulation of using switchover for two different
reference frequencies. In this example simulation, the reference clock is
either 100 or 66 MHz. The PLL begins with f_IN = 100 MHz and is allowed
to lock. At 20 s, the clock is switched to the secondary clock, which is at
66 MHz.
1–38
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009