EP2S130F1020I4 Datasheet, PDF (600/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Passive Serial Configuration
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Stratix II Device Handbook
or the Stratix II GX Device Handbook.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the MAX II device must generate a low-to-high
transition on the nCONFIG pin.
1
V_CCINT, V_CCIO, and V_CCPD of the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-k
pull-up resistor. Once nSTATUS is released, the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the MAX II device should place the configuration data one
bit at a time on the DATA0 pin. If you are using configuration data in RBF,
HEX, or TTF format, you must send the least significant bit (LSB) of each
data byte first. For example, if the RBF contains the byte sequence 02 1B
EE 01 FA, the serial bitstream you should transmit to the device is
0100-0000 1101-1000 0111-0111 1000-0000 0101-1111.
The Stratix II and Stratix II GX devices receive configuration data on the
DATA0 pin and the clock is received on the DCLK pin. Data is latched into
the device on the rising edge of DCLK. Data is continuously clocked into
the target device until CONF_DONE goes high. After the device has
received all configuration data successfully, it releases the open-drain
CONF_DONE pin, which is pulled high by an external 10-k pull-up
resistor. A low-to-high transition on CONF_DONE indicates configuration
is complete and initialization of the device can begin. The CONF_DONE
pin must have an external 10-k pull-up resistor in order for the device to
initialize.
In Stratix II and Stratix II GX devices, the initialization clock source is
either the internal oscillator (typically 10 MHz) or the optional CLKUSR
pin. By default, the internal oscillator is the clock source for initialization.
If the internal oscillator is used, the Stratix II or Stratix II GX device
provides itself with enough clock cycles for proper initialization.
Therefore, if the internal oscillator is the initialization clock source,
sending the entire configuration file to the device is sufficient to configure
and initialize the device. Driving DCLK to the device after configuration is
complete does not affect device operation.
7–48
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008