EP2S130F1020I4 Datasheet, PDF (467/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–5 shows the list of output standards that support on-chip series
termination without calibration.
Table 4–5. Selectable I/O Drivers with On-Chip Series Termination without
Calibration
I/O Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.2-V HSTL (1)
On-chip Series Termination Setting
Row I/O
50
25
50
25
50
25
50
25
50
50
50
50
50
25
50
50
50
Column I/O
Unit
50

25

50

25

50

25

50

25

50

25

50

25

50

50

50

25

50

25

50

25

50

50

Note to Table 4–5:
(1) 1.2-V HSTL is only supported in I/O banks 4,7, and 8.
To use on-chip termination for the SSTL Class I standard, users should
select the 50- on-chip series termination setting for replacing the
external 25- R_S (to match the 50- transmission line). For the
SSTL Class II standard, users should select the 25- on-chip series
termination setting (to match the 50- transmission line and the near end
50- pull-up to V_TT).
4–29
Stratix II Device Handbook, Volume 2