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EP2S130F1020I4 Datasheet, PDF (750/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1
Routing Schemes for Minimizing Crosstalk & Maintaining Signal Integrity
Single-Ended Trace Routing
A single-ended trace connects the source and the load/receiver.
Single-ended traces are used in general point-to-point routing, clock
routing, low-speed, and non-critical I/O routing. This section discusses
different routing schemes for clock signals. You can use the following
types of routing to drive multiple devices with the same clock:
■ Daisy chain routing
● With stub
● Without stub
■ Star routing
■ Serpentine routing
Use the following guidelines to improve the clock transmission line’s
signal integrity:
■ Keep clock traces as straight as possible. Use arc-shaped traces
instead of right-angle bends.
■ Do not use multiple signal layers for clock signals.
■ Do not use vias in clock transmission lines. Vias can cause impedance
change and reflection.
■ Place a ground plane next to the outer layer to minimize noise. If you
use an inner layer to route the clock trace, sandwich the layer
between reference planes.
■ Terminate clock signals to minimize reflection.
■ Use point-to-point clock traces as much as possible.
Daisy Chain Routing With Stubs
Daisy chain routing is a common practice in designing PCBs. One
disadvantage of daisy chain routing is that stubs, or short traces, are
usually necessary to connect devices to the main bus (see Figure 11–14). If
a stub is too long, it will induce transmission line reflections and degrade
signal quality. Therefore, the stub length should not exceed the following
conditions:
TDstub < (T10% to 90%)/3
where TDstub = Electrical delay of the stub
T10% to 90% = Rise or fall time of signal edge
For a 1-ns rise-time edge, the stub length should be less than 0.5 inches
(see the “References” section). If your design uses multiple devices, all
stub lengths should be equal to minimize clock skew.
11–14
Stratix II Device Handbook, Volume 2
Altera Corporation
May 2007