EP2S130F1020I4 Datasheet, PDF (633/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
PPA Configuration Timing
Figure 7–33 shows the timing waveform for the PPA configuration
scheme using a microprocessor.
Figure 7–33. Stratix II and Stratix II GX PPA Configuration Timing Waveform Using nWS
t_CFG t_CF2ST1
Note (1)
nCONFIG
nSTATUS (2)
CONF_DONE (3)
DATA[7..0]
(4) CS
(4) nCS
nWS
RDYnBSY
t_STATUS
t_CF2ST0
t_CF2CD
User I/Os
INIT_DONE
Byte 0
t_DSU
t_CF2WS
t_DH
Byte 1
t_WSP
t_RDY2WS
t_WS2B
High-Z
Byte n − 1
Byte n
t_CSSU ^tCSH
t_BUSY
High-Z
(5)
(5)
(5)
(5)
(5)
t_CD2UM
User-Mode
Notes to Figure 7–33:
(1) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(2) Upon power-up, Stratix II and Stratix II GX devices hold nSTATUS low for the time of the POR delay.
(3) Upon power-up, before and during configuration, CONF_DONE is low.
(4) The user can toggle nCS or CS during configuration if the design meets the specification for t_CSSU, t_WSP, and t_CSH.
(5) DATA[7..0], CS, nCS, nWS, nRS, and RDYnBSY are available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
Altera Corporation
January 2008
7–81
Stratix II Device Handbook, Volume 2