EP2S130F1020I4 Datasheet, PDF (698/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

IEEE Std. 1149.1 Boundary-Scan Register
Figure 9–4 shows the Stratix II and Stratix II GX device’s user I/O
boundary-scan cell.
Figure 9–4. Stratix II and Stratix II GX Device's User I/O BSC with IEEE Std. 1149.1 BST Circuitry
Capture
Registers
Update
Registers
SDO
INJ
PIN_IN
0
0
DQ
DQ
1
1
INPUT
INPUT
From or
OEJ
To Device
I/O Cell
Circuitry
And/Or
Logic
Array
OUTJ
0
0
DQ
DQ
1
0
1
OE
OE
1
V_CC
PIN_OE
0
DQ
DQ
1
OUTPUT
OUTPUT
0
PIN_OUT
Pin
1
Output
Buffer
SDI
SHIFT CLOCK
UPDATE HIGHZ MODE
Global
Signals
Table 9–2 describes the capture and update register capabilities of all
boundary-scan cells within Stratix II and Stratix II GX devices.
Table 9–2. Stratix II and Stratix II GX Device Boundary Scan Cell Descriptions (Part 1 of 2) Note (1)
Captures
Drives
Pin Type
Output
Capture
Register
OE
Input
Capture Capture
Register Register
Output
Update
Register
OE
Update
Register
Input
Update
Register
Comments
User I/O pins OUTJ
Dedicated clock 0
input
OEJ
PIN_IN PIN_OUT PIN_OE INJ
NA
1
PIN_IN N.C. (2) N.C. (2) N.C. (2) PIN_IN drives to
clock network or
logic array
9–6
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008