EP2S130F1020I4 Datasheet, PDF (212/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Timing Model
Table 5–76. Stratix II I/O Output Delay for Row Pins (Part 3 of 3)
I/O Standard
Drive
Strength
Parameter
Minimum Timing
Industrial Commercial
-3
Speed
Grade
(2)
-3
Speed
Grade
(3)
-4
Speed
Grade
-5
Speed
Grade
Unit
1.8-V HSTL
4 mA
t_{O P}
Class I
t_{D I P}
6 mA
t_{O P}
t_{D I P}
8 mA
t_{O P}
t_{D I P}
10 mA t_{O P}
t_{D I P}
12 mA t_{O P}
(1)
t_{D I P}
1.5-V HSTL
4 mA
t_{O P}
Class I
t_{D I P}
6 mA
t_{O P}
t_{D I P}
8 mA (1) t_{O P}
t_{D I P}
LVDS
t_{O P}
t_{D I P}
HyperTransport
t_{O P}
t_{D I P}
972
930
975
933
958
916
962
920
953
911
970
928
974
932
960
918
1018
976
1005
963
1019
976
1022
979
1004
961
1008
965
999
956
1018
975
1021
978
1006
963
1067
1024
1053
1010
1610 1689 1850 1956 ps
1555 1632 1787 1883 ps
1580 1658 1816 1920 ps
1525 1601 1753 1847 ps
1576 1653 1811 1916 ps
1521 1596 1748 1843 ps
1567 1644 1801 1905 ps
1512 1587 1738 1832 ps
1566 1643 1800 1904 ps
1511 1586 1737 1831 ps
1591 1669 1828 1933 ps
1536 1612 1765 1860 ps
1579 1657 1815 1919 ps
1524 1600 1752 1846 ps
1572 1649 1807 1911 ps
1517 1592 1744 1838 ps
1723 1808 1980 2089 ps
1668 1751 1917 2016 ps
1723 1808 1980 2089 ps
1668 1751 1917 2016 ps
Notes to Table 5–76:
(1) This is the default setting in the Quartus II software.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Maximum Input & Output Clock Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
5–66
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011