EP2S130F1020I4 Datasheet, PDF (354/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Clock Control Block
clkena Signals
Figure 1–55 shows how clkena is implemented.
Figure 1–55. clkena Implementation
clkena
clk
DQ
clkena_out
clk_out
In Stratix II devices, the clkena signals are supported at the clock
network level. This allows you to gate off the clock even when a PLL is
not being used.
The clkena signals can also be used to control the dedicated external
clocks from enhanced PLLs. Upon re-enabling, the PLL does not need a
resynchronization or relock period unless the PLL is using external
feedback mode. Figure 1–56 shows the waveform example for a clock
output enable. clkena is synchronous to the falling edge of the counter
output.
Figure 1–56. Clkena Signals
counter
output
clkena
clkout
Note to Figure 1–56
(1) The clkena signals can be used to enable or disable the global and regional networks or the PLL_OUT pins.
1–90
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009