EP2S130F1020I4 Datasheet, PDF (284/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Clock Feedback Modes
Table 1–11. Fast PLL Pins (Part 2 of 2) Note (1)
Pin
GNDA_PLL10
Description
Analog ground for PLL 10. You can connect this pin to the GND plane on the board.
Note to Table 1–11:
(1) The negative leg pins (CLKn and FPLL_CLKn) are only required with differential signaling.
Clock Feedback
Modes
Stratix II and Stratix II GX PLLs support up to five different clock
feedback modes. Each mode allows clock multiplication and division,
phase shifting, and programmable duty cycle. Each PLL must be driven
by one of its own dedicated clock input pins for proper clock
compensation. The clock input pin connections for each PLL are listed in
Table 1–20 on page 1–70.
Table 1–12 shows which modes are supported by which PLL type.
Table 1–12. Clock Feedback Mode Availability
Clock Feedback Mode
Source synchronous mode
No compensation mode
Normal mode
Zero delay buffer mode
External feedback mode
Mode Available in
Enhanced PLLs
Fast PLLs
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Source-Synchronous Mode
If data and clock arrive at the same time at the input pins, they are
guaranteed to keep the same phase relationship at the clock and data
ports of any IOE input register. Figure 1–9 shows an example waveform
of the clock and data in this mode. This mode is recommended for source-
synchronous data transfers. Data and clock signals at the IOE experience
similar buffer delays as long as the same I/O standard is used.
1–20
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009