EP2S130F1020I4 Datasheet, PDF (544/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Operational Modes
multiplication operations using eight 9-bit multipliers feeding four
adder/subtractor/accumulator blocks. Resources external to the DSP
block must be used to route the correct real and imaginary input
components to the appropriate multiplier inputs to perform the correct
computation for the complex multiplication operation.
Figure 6–12. Complex Multiplier Using Two-Multiplier Adder Mode
18
18
18
18
DSP Block
18
A
36
18
C
18
B
18
D
37
Subtractor
36
18
A
36
18
D
18
B
18
C
37
Adder
36
(A × C) − (B × D)
(Real Part)
(A × D) + (B × C)
(Imaginary Part)
Four-Multiplier Adder
In the four-multiplier adder configuration, the DSP block can implement
one 18 × 18 or two individual 9 × 9 multiplier adders. These modes are
useful for implementing one-dimensional and two-dimensional filtering
applications. The four-multiplier adder is performed in two addition
stages. The outputs of two of the four multipliers are initially summed in
the two first-stage adder/subtractor/accumulator blocks. The results of
these two adder/subtractor/accumulator blocks are then summed in the
final stage summation block to produce the final four-multiplier adder
result. Figure 6–13 shows the DSP block configured in the four-multiplier
adder mode.
6–28
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008