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EP2S130F1020I4 Datasheet, PDF (626/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1
Passive Parallel Asynchronous Configuration
Figure 7–30. Single Device PPA Configuration Using a Microprocessor
Address Decoder
ADDR
VCC (2)
Memory
ADDR DATA[7..0]
Microprocessor
10 kΩ
VCC (2)
Stratix II or Stratix II GX
10 k Ω
Device
nCS (1)
MSEL3
VCC
CS (1)
MSEL2
CONF_DONE MSEL1
nSTATUS
MSEL0
nCE
GND
DATA[7..0]
nCEO N.C. GND
VCC (2)
nWS
nRS
10 kΩ
nCONFIG
RDYnBSY
DCLK
Notes to Figure 7–30:
(1) If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
(2) The pull-up resistor should be connected to a supply that provides an acceptable input signal for the device. VCC
should be high enough to meet the VIH specification of the I/O on the device and the external host.
During PPA configuration, it is only required to use either the nCS or CS
pin. Therefore, if you are using only one chip-select input, the other must
be tied to the active state. For example, nCS can be tied to ground while
CS is toggled to control configuration. The device’s nCS or CS pins can be
toggled during PPA configuration if the design meets the specifications
set for tCSSU, tWSP, and tCSH listed in Table 7–18.
Upon power-up, the Stratix II and Stratix II GX devices go through a
POR. The POR delay is dependent on the PORSEL pin setting. When
PORSEL is driven low, the POR time is approximately 100 ms. If PORSEL
is driven high, the POR time is approximately 12 ms. During POR, the
device will reset, hold nSTATUS low, and tri-state all user I/O pins. Once
the device successfully exits POR, all user I/O pins continue to be
tri-stated. If nIO_pullup is driven low during power-up and
configuration, the user I/O pins and dual-purpose I/O pins will have
weak pull-up resistors which are on (after POR) before and during
configuration. If nIO_pullup is driven high, the weak pull-up resistors
are disabled.
7–74
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008