EP2S130F1020I4 Datasheet, PDF (417/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

External Memory Interfaces in Stratix II and Stratix II GX Devices
and DDR2 SDRAM devices requires a DM pin. There is one DM pin per
RLDRAM II device. The DDR I/O output registers, clocked by the –90°
shifted clock, creates the DM signals, similar to DQ output signals.
1 Perform timing analysis to calculate your write-clock phase
shift.
Some DDR SDRAM and DDR2 SDRAM devices support error correction
coding (ECC), which is a method of detecting and automatically
correcting errors in data transmission. In a 72-bit DDR SDRAM interface,
there are eight ECC pins in addition to the 64 data pins. Connect the DDR
and DDR2 SDRAM ECC pins to a Stratix II or Stratix II GX device
DQS/DQ group. The memory controller needs extra logic to encode and
decode the ECC data.
QVLD pins are used in RLDRAM II interfacing to indicate the read data
availability. There is one QVLD pin per RLDRAM II device. A high on
QVLD indicates that the memory is outputting the data requested.
Similar to DQ inputs, this signal is edge-aligned with QK/QK# signals
and is sent half a clock cycle before data starts coming out of the memory.
You need to connect QVLD pins to the DQVLD pin on the Stratix II or
Stratix II GX device. The DQVLD pin can be used as a regular user I/O
pin if not used for QVLD. Because the Quartus II software does not
differentiate DQVLD pins from DQ pins, you must ensure that your
design uses the pin table’s recommended DQVLD pin.
DQS Phase-Shift Circuitry
The Stratix II or Stratix II GX phase-shift circuitry and the DQS logic
block control the DQS and DQSn pins. Each Stratix II or Stratix II GX
device contains two phase-shifting circuits. There is one circuit for I/O
banks 3 and 4, and another circuit for I/O banks 7 and 8. The phase-
shifting circuit on the top of the device can control all the DQS and DQSn
pins in the top I/O banks and the phase-shifting circuit on the bottom of
the device can control all the DQS and DQSn pins in the bottom I/O
banks. Figure 3–8 shows the DQS and DQSn pin connections to the DQS
logic block and the DQS phase-shift circuitry.
Altera Corporation
January 2008
3–21
Stratix II Device Handbook, Volume 2