EP2S130F1020I4 Datasheet, PDF (276/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Enhanced PLLs
Table 1–5. Enhanced PLL Output Signals (Part 2 of 2)
Port
scandataout
scandone
Description
Source
Output of the last shift register in the PLL scan chain
scan chain.
Signal indicating when the PLL has
completed reconfiguration. 1 to 0
transition indicates that the PLL has
been reconfigured.
PLL scan chain
Destination
Logic array
Logic array
Enhanced PLL Pins
Table 1–6 lists the I/O standards support by the enhanced PLL clock
outputs.
Table 1–6. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2)
Note (1)
I/O Standard
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL Class I
1.2-V HSTL Class II
Input
INCLK
FBIN
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Output
EXTCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
1–12
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009