EP2S130F1020I4 Datasheet, PDF (712/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Disabling IEEE Std. 1149.1 BST Circuitry
2. Click Assembler.
3. Turn on Always Enable Input Buffers.
Disabling IEEE
Std. 1149.1 BST
Circuitry
The IEEE Std. 1149.1 BST circuitry for Stratix II and Stratix II GX devices
is enabled upon device power-up. Because the IEEE Std. 1149.1 BST
circuitry is used for BST or in-circuit reconfiguration, you must enable the
circuitry only at specific times as mentioned in, “Using IEEE Std. 1149.1
BST Circuitry” on page 9–19.
1 If you are not using the IEEE Std. 1149.1 circuitry in Stratix II or
Stratix II GX, then you should permanently disable the circuitry
to ensure that you do not inadvertently enable when it is not
required.
Table 9–4 shows the pin connections necessary for disabling the IEEE Std.
1149.1 circuitry in Stratix II and Stratix II GX devices.
Table 9–4. Disabling IEEE Std. 1149.1 Circuitry
JTAG Pins (1)
TMS
TCK
TDI
TDO
TRST
Connection for Disabling
V_{C C}
GND
V_{C C}
Leave open
GND
Note to Table 9–4:
(1) There is no software option to disable JTAG in Stratix II or Stratix II GX devices.
The JTAG pins are dedicated.
Guidelines for
IEEE Std. 1149.1
Boundary-Scan
Testing
Use the following guidelines when performing boundary-scan testing
with IEEE Std. 1149.1 devices:
■ If the “10...” pattern does not shift out of the instruction register via
the TDO pin during the first clock cycle of the SHIFT_IR state, the
TAP controller did not reach the proper state. To solve this problem,
try one of the following procedures:
● Verify that the TAP controller has reached the SHIFT_IR state
correctly. To advance the TAP controller to the SHIFT_IR state,
return to the RESET state and send the code 01100 to the TMS
pin.
9–20
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008