EP2S130F1020I4 Datasheet, PDF (447/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Selectable I/O Standards in Stratix II and Stratix II GX Devices
Figure 4–5. 1.8-V HSTL Class I Termination
Output Buffer
V_TT = 0.9 V
Z = 50 Ω
50 Ω
V_REF = 0.9 V
Input Buffer
Figure 4–6. 1.8-V HSTL Class II Termination
V_TT = 0.9 V
V_TT = 0.9 V
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
V_REF = 0.9 V
Input Buffer
1.5-V HSTL Class I and 1.5-V HSTL Class II
The 1.5-V HSTL standard is formulated under EIA/JEDEC Standard,
EIA/JESD8-6: A 1.5-V Output Buffer Supply Voltage Based Interface
Standard for Digital Integrated Circuits.
The 1.5-V HSTL I/O standard is used for applications designed to operate
in the 0.0- to 1.5-V HSTL logic nominal switching range. This standard
defines single-ended input and output specifications for all
HSTL-compliant digital integrated circuits. The 1.5-V HSTL I/O standard
in Stratix II and Stratix II GX devices are compatible with the 1.8-V HSTL
I/O standard in APEX™ 20KE, APEX 20KC, and in Stratix II and
Stratix II GX devices themselves because the input and output voltage
thresholds are compatible (Figures 4–7 and 4–8).
1
Stratix II and Stratix II GX devices support both input and
output levels with V_REF and V_TT.
Altera Corporation
January 2008
4–9
Stratix II Device Handbook, Volume 2