EP2S130F1020I4 Datasheet, PDF (305/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
Figure 1–24. Manual Switchover Note (1)
inclk0
inclk1
muxout
clkswitch
Note to Figure 1–24:
(1) Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate a manual clock
switchover event. Failing to meet this requirement causes the clock switchover to not function properly.
Software Support
Table 1–15 summarizes the signals used for clock switchover.
Table 1–15. altpll Megafunction Clock Switchover Signals (Part 1 of 2)
Port
inclk0
inclk1
clkbad0(1)
clkbad1(1)
clkswitch
clkloss(1)
locked
Description
Source
Destination
Reference clk0 to the PLL.
I/O pin
Clock switchover circuit
Reference clk1 to the PLL.
I/O pin
Clock switchover circuit
Signal indicating that inclk0 is no longer Clock switchover
toggling.
circuit
Logic array
Signal indicating that inclk1 is no longer Clock switchover
toggling.
circuit
Logic array
Switchover signal used to initiate clock
switchover asynchronously. When used in
manual switchover, clkswitch is used as a
select signal between inclk0 and inclk1
clswitch = 0 inclk0 is selected
and vice versa.
Logic array or I/O pin
Clock switchover circuit
Signal indicating that the switchover
circuit detected a switch condition.
Clock switchover
circuit
Logic array
Signal indicating that the PLL has lost PLL
lock.
Clock switchover circuit
Altera Corporation
July 2009
1–41
Stratix II Device Handbook, Volume 2