EP2S130F1020I4 Datasheet, PDF (477/768 Pages) List of Unclassifed Manufacturers – Stratix II Device Handbook, Volume 1

Selectable I/O Standards in Stratix II and Stratix II GX Devices
single-ended outputs must be placed at least one LAB row away from the
differential I/O pins. There are no restrictions on the placement of
single-ended input pins with respect to differential I/O pins.
Single-ended input pins may be placed within the same LAB row as
differential I/O pins. However, the single-ended input’s IOE register is
not available. The input must be implemented within the core logic.
This single-ended output pin placement restriction only applies when
using the LVDS or HyperTransport I/O standards in the left and right
I/O banks. There are no restrictions for single-ended output pin
placement with respect to differential clock pins in the top and bottom
I/O banks.
Figure 4–25. Single-Ended Output Pin Placement with Respect to Differential
I/O Pins
Single-Ended Output Pin
Differential I/O Pin
Single_Ended Input
Single-Ended Outputs
Not Allowed
Row Boundary
Altera Corporation
January 2008
DC Guidelines
Power budgets are essential to ensure the reliability and functionality of
a system application. You are often required to perform power
dissipation analysis on each device in the system to come out with the
total power dissipated in that system, which is composed of a static
component and a dynamic component.
The static power consumption of a device is the total DC current flowing
from V_CCIO to ground.
4–39
Stratix II Device Handbook, Volume 2