XC3S50 Datasheet, PDF (99/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: Pinout Descriptions
R
One of eight
I/O Banks
User I/O
User I/O
One of eight
I/O Banks
VRN
VRP
R_REF (1%)
One of eight
I/O Banks
VRN
VRP
VCCO
R_REF (1%)
R_REF (1%)
(a) No termination
(b) Single termination
(c) Split termination
Figure 3: DCI Termination Types
DS099-4_03_071304
PROG_B: Program/Configure Device
This asynchronous pin initiates the configuration or re-con-
figuration processes. A Low-going pulse resets the configu-
ration logic, initializing the configuration memory. This
initialization process cannot finish until PROG_B returns
High. Asserting PROG_B Low for an extended period
delays the configuration process. At power-up, there is
always a weak pull-up resistor to VCCAUX on this pin. After
configuration, the bitstream generator option ProgPin deter-
mines whether or not the weak pull-up resistor is present.
By default, the ProgPin option retains the weak pull-up
resistor.
After configuration, hold the PROG_B input High. Any
Low-going pulse on PROG_B restarts the configuration pro-
cess.
Table 5: PROG_B Operation
PROG_B Input
Response
Power-up
Automatically initiates configuration
process.
Low-going pulse Initiate (re-)configuration process and
continue to completion.
Extended Low
1
Initiate (re-)configuration process and
stall process at step where
configuration memory is cleared.
Process is stalled until PROG_B
returns High.
If the configuration process is started,
continue to completion. If
configuration process is complete,
stay in User mode.
DONE: Configuration Done, Delay Start-Up
Sequence
The FPGA produces a Low-to-High transition on this pin
indicating that the configuration process is complete. The
bitstream generator option DriveDone determines whether
this pin functions as a totem-pole output that can drive High
or as an open-drain output. If configured as an open-drain
output—which is the default behavior—then a pull-up resis-
tor is required to produce a High logic level. There is a bit-
stream option that provides an internal weak pull-up
resistor, otherwise an external pull-up resistor is required.
The open-drain option permits the DONE lines of multiple
FPGAs to be tied together, so that the common node transi-
tions High only after all of the FPGAs have completed con-
figuration. Externally holding the open-drain DONE pin Low
delays the start-up sequence, which marks the transition to
user mode.
Once the FPGA enters User mode after completing config-
uration, the DONE pin no longer drives the DONE pin Low.
The bitstream generator option DonePin determines
whether or not a weak pull-up resistor is present on the
DONE pin to pull the pin to VCCAUX. If the weak pull-up
resistor is eliminated, then the DONE pin must be pulled
High using an external pull-up resistor or one of the FPGAs
in the design must actively drive the DONE pin High via the
DriveDone bitstream generator option.
The bitstream generator option DriveDone causes the
FPGA to actively drive the DONE output High after configu-
ration. This option should only be used in single-FPGA
designs or on the last FPGA in a multi-FPGA daisy-chain.
By default, the bitstream generator software retains the
weak pull-up resistor and does not actively drive the DONE
pin as highlighted in Table 6. Table 6 shows the interaction
of these bitstream options in single- and multi-FPGA
designs.
12
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DS099-4 (v1.5) July 13, 2004
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Product Specification