XC3S50 Datasheet, PDF (109/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: Pinout Descriptions
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Detailed mechanical drawings for each package type are
available from the Xilinx website at the specified location in
Table 13.
Table 13: Xilinx Package Mechanical Drawings
Package
Web Link (URL)
VQ100 / VQG100 http://www.xilinx.com/bvdocs/packages/vq100.pdf
TQ144 / TQG144 http://www.xilinx.com/bvdocs/packages/tq144.pdf
PQ208 / PQG208 http://www.xilinx.com/bvdocs/packages/pq208.pdf
FT256 / FTG256 http://www.xilinx.com/bvdocs/packages/ft256.pdf
FG320 / FGG320 http://www.xilinx.com/bvdocs/packages/fg320.pdf
FG456 / FGG456 http://www.xilinx.com/bvdocs/packages/fg456.pdf
FG676 / FGG676 http://www.xilinx.com/bvdocs/packages/fg676.pdf
FG900 /FGG900 http://www.xilinx.com/bvdocs/packages/fg900.pdf
FG1156 / FGG1156 http://www.xilinx.com/bvdocs/packages/fg1156.pdf
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions varies by package, as shown in Table 14.
Table 14: Power and Ground Supply Pins by Package
Package VCCINT VCCAUX VCCO GND
VQ100
4
4
8
10
TQ144
4
4
12
16
PQ208
4
8
12
28
FT256
8
8
24
32
FG320
12
8
28
40
FG456
12
8
40
52
FG676
20
16
64
76
FG900
32
24
80
120
FG1156
40
32
104
184
A majority of package pins are user-defined I/O pins. How-
ever, the numbers and characteristics of these I/O depends
on the device type and the package in which it is available,
as shown in Table 15. The table shows the maximum num-
ber of single-ended I/O pins available, assuming that all
I/O-, DUAL-, DCI-, VREF-, and GCLK-type pins are used as
general-purpose I/O. Likewise, the table shows the maxi-
mum number of differential pin-pairs available on the pack-
age. Finally, the table shows how the total maximum user
I/Os are distributed by pin type, including the number of
unconnected—i.e., N.C.—pins on the device.
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